Silicon Design Verification Engineer
Akkodis is seeking a skilled Silicon Design Verification Engineer to work on-site with our client in Philadelphia, PA.
As the successful candidate, you will be responsible for developing formal test plans, executing complete formal verification sign-off of single or multiple complex blocks, and partnering with cross-functional teams towards creating a first-pass silicon success.
This is an excellent opportunity to grow your career while working on exciting projects with a dynamic team!
Responsibilities:
o Develop comprehensive formal test plans o Execute complete formal verification sign-off of single or multiple complex blocks o Partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success o Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level o Work with Architecture and Design team to come up with Formal driven specification and implementation o Define formal verification scope, create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level o Build reusable/scalable environments for Formal Verification and deploying the tools o Evaluate and recommend EDA solutions for Formal Verification o Provide training for internal teams and mentoring engineers related to Formal Verification TechnologySkills:
o A minimum of three years of experience with SoC Design Verification o Bachelor's Degree or equivalent (12 years) work experience (If an Associates Degree with 6 years of work experience)Bonus points if:
o Experience with PCIe Verification o Experience with ARM Cortex In-depth knowledge of digital logic design, chip architecture and microarchitecture o Experience in developing TestPlan/testbenches, SystemVerilog/UVM/C-based TestBench, and writing/debugging tests Experience with advanced verification techniques such as different booting verification,end-to-end verification;multiple CPUs verification as part of the IP is desirable.
o Experience in ARM AMBA protocols; AXI4,AHB and APB.
Candidate Description:
The ideal candidate should have:
o A strong understanding of Linear/non-linear state estimation theory Familiarity with relative navigation concepts Knowledge in the design, analysis, and implementation of navigation algorithms The ability to solve complex total GN&C system problems o Experience programming in C/C++and knowledge of Matlab/Simulink o Excellent communication skills o Strong team player o Minimum MS in Aerospace,Mechanical or Electrical Engineering preferred o Knowledge of image processing preferred o Knowledge of inertial sensors preferredIf you are interested in this Silicon Design Verification Engineer at Philadelphia, PA, please contact Nisha Kashyap at 213-567-9083 or nisha.
kashyap@akkodis.
comPay Details:
$70.
00 to $75.
00 per hour Benefit offerings available for our associates include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, EAP program, commuter benefits and a 401K plan.
Our benefit offerings provide employees the flexibility to choose the type of coverage that meets their individual needs.
In addition, our associates may be eligible for paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law, as well as Holiday pay where applicable.
Equal Opportunity Employer/Veterans/DisabledTo read our Candidate Privacy Information Statement, which explains how we will use your information, please navigate to https:
//www.
modis.
com/en-us/candidate-privacy />The Company will consider qualified applicants with arrest and conviction records subject to federal contractor requirements and/or security clearance requirements.
Recommended Skills Arm Architecture Aerospace Industries Algorithms Architecture Coaching And Mentoring Communication Estimated Salary: $20 to $28 per hour based on qualifications.
As the successful candidate, you will be responsible for developing formal test plans, executing complete formal verification sign-off of single or multiple complex blocks, and partnering with cross-functional teams towards creating a first-pass silicon success.
This is an excellent opportunity to grow your career while working on exciting projects with a dynamic team!
Responsibilities:
o Develop comprehensive formal test plans o Execute complete formal verification sign-off of single or multiple complex blocks o Partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success o Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level o Work with Architecture and Design team to come up with Formal driven specification and implementation o Define formal verification scope, create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level o Build reusable/scalable environments for Formal Verification and deploying the tools o Evaluate and recommend EDA solutions for Formal Verification o Provide training for internal teams and mentoring engineers related to Formal Verification TechnologySkills:
o A minimum of three years of experience with SoC Design Verification o Bachelor's Degree or equivalent (12 years) work experience (If an Associates Degree with 6 years of work experience)Bonus points if:
o Experience with PCIe Verification o Experience with ARM Cortex In-depth knowledge of digital logic design, chip architecture and microarchitecture o Experience in developing TestPlan/testbenches, SystemVerilog/UVM/C-based TestBench, and writing/debugging tests Experience with advanced verification techniques such as different booting verification,end-to-end verification;multiple CPUs verification as part of the IP is desirable.
o Experience in ARM AMBA protocols; AXI4,AHB and APB.
Candidate Description:
The ideal candidate should have:
o A strong understanding of Linear/non-linear state estimation theory Familiarity with relative navigation concepts Knowledge in the design, analysis, and implementation of navigation algorithms The ability to solve complex total GN&C system problems o Experience programming in C/C++and knowledge of Matlab/Simulink o Excellent communication skills o Strong team player o Minimum MS in Aerospace,Mechanical or Electrical Engineering preferred o Knowledge of image processing preferred o Knowledge of inertial sensors preferredIf you are interested in this Silicon Design Verification Engineer at Philadelphia, PA, please contact Nisha Kashyap at 213-567-9083 or nisha.
kashyap@akkodis.
comPay Details:
$70.
00 to $75.
00 per hour Benefit offerings available for our associates include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, EAP program, commuter benefits and a 401K plan.
Our benefit offerings provide employees the flexibility to choose the type of coverage that meets their individual needs.
In addition, our associates may be eligible for paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law, as well as Holiday pay where applicable.
Equal Opportunity Employer/Veterans/DisabledTo read our Candidate Privacy Information Statement, which explains how we will use your information, please navigate to https:
//www.
modis.
com/en-us/candidate-privacy />The Company will consider qualified applicants with arrest and conviction records subject to federal contractor requirements and/or security clearance requirements.
Recommended Skills Arm Architecture Aerospace Industries Algorithms Architecture Coaching And Mentoring Communication Estimated Salary: $20 to $28 per hour based on qualifications.
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